The present invention generally relates to buffer circuits, and more particularly to an input buffer circuit for converting a logic level of an input signal having an ECL (emitter-coupled-logic) level to a signal having a logic level suitable for use in a compound semiconductor integrated circuit.
There are various semiconductor devices such as bipolar ECL devices, n-MOS (metal-oxide-semiconductor) devices, GaAs MESFET (gallium arsenide metal-semiconductor field effect transistor) devices, HEMT (high electron mobility transistor) devices and the like that are used in high speed logic integrated circuits. Among others, silicon-based bipolar ECL devices are used most commonly.
Generally, the logic level (voltage level) used in the silicon-based ECL device, called the ECL level, is different from the logic level used in the compound semiconductor devices such as GaAs MESFET or HEMT. Therefore, there is a need to achieve compatibility between the logic levels when devices of different types are used in a same system.
For example, when a part of a high speed arithmetic unit using ECL devices is to be replaced by MESFET or HEMT devices, an input/output buffer circuit is needed for achieving compatibility between the ECL device and the other devices. Such an input/output buffer circuit is required to have a characteristic which is stable against variation of the characteristics of the semiconductor devices used therein.
There are a number of designs for high speed logic gates of GaAs integrated circuits that are developed so as to meet various requirements such as low electrical power, short delay time, large scale of integration, appropriate source voltage level, appropriate logic amplitude, high operational frequency, easy manufacturing process, high yield, and the like. From the view point of large scale integration and low power consumption, integrated circuits of FET devices are preferred and various devices such as HEMT or GaAs MESFET are studied intensively.
While there are various designs for the logic circuit based on the FET of GaAs or other compound semiconductor integrated circuits, a DCFL (direct coupled FET logic) device comprising an enhancement type FET and a depletion type FET acting as a load of the enhancement type FET is particularly preferred from the view point of integration density, simple construction, small size, low power consumption, high operational speed and the like. Thus, the DCFL device is expected to play a major role in the logic gates of the future LSI (large scale integrated circuit) or VLSI (very large scale integrated circuit) devices.
As already noted, there is a need to provide an input buffer circuit to achieve compatibility of the logic level of the signals when the DCFL or other compound semiconductor device is used in combination with the ECL device.
Conventionally three types of input buffer circuits are known for achieving compatibility between the ECL device and the DCFL device.
Referring to FIGS. 1 and 2 at first, the first type of the prior art input buffer circuit uses two depletion type FETs and an inverter circuit in combination for producing a signal to be supplied to the following circuit which may be the DCFL device. As shown in FIG. 1, the buffer circuit represented by a circuit 1 comprises a level shift circuit 2 and an inverter 3. The level shift circuit 2 comprises a pair of depletion type FETs 4 and 5 connected in series, in which a source of the FET 4 is connected to a drain of the FET 5, a gate and a source of the FET 5 are connected each other, and a drain of the FET 4 is connected to the ground. The source of the FET 5 is further connected to a constant voltage source supplying a source voltage of -3.6 volts. The inverter 3, on the other hand, comprises a depletion type FET 6 and an enhancement type FET 7 connected in series, wherein a source of the FET 6 is connected to a drain of the FET 7, a drain of the FET 6 is connected to the ground, and a source of the FET 7 is connected to a constant voltage source supplying a source voltage of -2 volts. Further, the source of the FET 4 is connected to a gate of the FET 7. Thus, the level shift circuit 2 shifts the level of an input signal having the ECL level applied to a gate of the FET 4 and a signal having a level adapted to the following circuit is produced after inversion in the inverter 3. In this circuit 1, one can change the amount of shift by choosing a gate width of the FETs 4 and 5. Further, one can obtain a buffering operation by setting the gate width of the FETs 6 and 7 properly so that the current flowing through these FETs is increased.
This prior art buffer circuit 1, however, has the following problems.